1. Field of the Invention
The present invention relates generally to the field of semiconductor device fabrication, and more particularly to the field of bump processing for semiconductor device fabrication.
2. Description of the Related Art
Typically in semiconductor device fabrication, various semiconductor devices are formed over the surface of a semiconductor substrate in accordance with design and/or functional requirements for a desired semiconductor integrated circuit. Once these semiconductor devices have been formed, a passivation layer is put down over the surface of the wafer to seal the devices from contaminants and moisture and, generally, to protect the wafer from being damaged, for example, from scratching. This passivation layer is subsequently etched to expose specific metallization patterns, or "bonding pads," in the underlying device layers. These exposed bonding pads may later be connected to the lead frame of a chip carrier so as to provide for electrical connection to the device circuitry from outside the chip.
In order to establish these chip connections, "bumps" may be formed over the bonding pads. These bumps are typically formed prior to testing the device circuitry since the probing of the bonding pads used in such testing causes the material in the bonding pads to "roll up" and form probe marks on the surface of the bonding pads. Typically, these probe marks cannot be completely covered by a subsequently deposited barrier layer due to poor step coverage of this barrier layer over the probe marks. If a bump were to then be formed over the barrier layer of a given probed bonding pad and later annealed using typical annealing processes, excessive intermetallic elements would form between the bump and the probed bonding pad. Such excessive intermetallic formation would cause long term reliability problems since these intermetallic elements are brittle by nature, thus making the interface between the bump and the bonding pad fragile. Furthermore, Kirkendall voids would form at the interface of the bump and the probed bonding pad during the typical annealing process. This void formation would weaken the interface between the bump and the bonding pad and hence further reduce the reliability of the interconnect structure. As a consequence of typical bump annealing processes, then, the probing of wafers prior to bumping would prove to be ineffectual because of these long term reliability concerns.
One solution to avoid the above reliability problems is to test the semiconductor devices after the bonding pads have been bumped. That is, the probes used in testing the devices are directly or indirectly coupled to the bumps formed over the bonding pads as opposed to being coupled directly to the bonding pads prior to bumping. Without probe marks over the bonding pads, then, the overlying barrier layer has better step coverage over each bonding pad, thus preventing excessive intermetallic formation between the bump and the bonding pad during the bump annealing process. Although this process avoids the reliability problems caused when the bonding pads are directly probed during testing, it is more costly and wastes process steps. For example, if a wafer is bumped prior to testing and only later proves to have a zero or very low yield of properly functioning devices, most if not all of the cost, time, and processing incurred in bumping this low yield wafer has dearly been wasted. Had the wafer been tested prior to bumping, the discovery of its low yield would have prevented this waste.
Thus, what is needed is an improved process for bumping wafers to reduce or eliminate the intermixing of materials between the bonding pad and the bump when the bump is being annealed so as to provide for a more reliable and durable interconnection between the bump and the bonding pad. What if also needed is an improved process for probing wafers prior to bumping so that the cost, time, and processing efforts typically incurred in bumping wafers having a zero or low yield of properly functioning devices may be saved.